The present disclosure relates to a graphene device, and particularly to a graphene transistor having a self-aligned gate and methods of manufacturing the same.
The high mobility of charge carriers in graphene combined with the ability to modulate the carrier concentration by an external electric field has made graphene-based field effect transistors (FETs), or “graphene FETs,” promising candidates for future high frequency applications. Recently, graphene FETs have been demonstrated to operate at cut-off frequencies (fT) as high as 100 GHz. Additional increases in fT may be achievable through further improvement of both the constituent device materials and the device design. One of the critical factors currently limiting the performance of graphene FETs is the parasitic series resistance between the source/drain contacts and the gated graphene channel.
Graphene FETs include access regions in a graphene layer, which are between a gate and source/drain electrodes of a graphene-based field effect transistor. The access regions serve to reduce the parasitic capacitance between the gate and the source/drain electrodes. However, the access regions inevitably increase the resistance of the graphene FET, thereby reducing the current through the graphene FETs and limiting the device performance. It is therefore desirable to minimize as much as possible the access resistance (RA), which is the resistance of the access regions of a graphene FET. Reduction of the access resistance is especially crucial to scale down graphene devices because the access resistance can become comparable to the resistance of the gated channel and adversely affect the device behavior significantly as the device dimensions shrink.
The access resistance of conventional silicon-based FETs can be reduced by doping ungated regions through ion implantation to form source/drain regions having a high electrical conductivity. For example, a silicon nitride spacer can be deposited along the sidewall of a gate electrode, followed by the formation of highly doped source/drain regions by ion implantation. In the case of a graphene transistor, however, ion implantation cannot be employed because implanted dopant ions readily and inevitably destroy the fragile lattice structure of the graphene layer.